MT-086: Fundamentals of Phase Locked Loops (PLLs)
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چکیده
Referring to Figure 1, a system for using a PLL to generate higher frequencies than the input, the VCO oscillates at an angular frequency of ωO. A portion of this signal is fed back to the error detector, via a frequency divider with a ratio 1/N. This divided down frequency is fed to one input of the error detector. The other input in this example is a fixed reference signal. The error detector compares the signals at both inputs. When the two signal inputs are equal in phase and frequency, the error will be constant and the loop is said to be in a “locked” condition.
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